1. The Field of the Invention
The present invention relates to wafer-scale integrated circuits where one or more ports are provided together with a plurality of data processing cells on a semiconductor wafer substrate. In particular, the present invention relates to a method and apparatus for distributing control signals to the cells.
2. The Prior Art
The wafer whereon the cells and port or ports are fabricated is generally several inches in diameter. In order that the cell fabrication failure rate may be accomodated on the wafer, the interconnection between the cells is left indeterminate, each cell being provided with means whereby it can be coupled to any selectable neighbouring cell. Starting at one or more of the ports, cells adjacent to the port or ports are tested and, if functional, coupled to the port or ports. Thereafter the the coupled cell or cells couple to and test neighbouring cells which are similarly incorporated if they prove functional. Cells which do not pass the functional test are not coupled into the overall function of the circuit, other functional cells being found to take their places. At the end of the test and coupling process one or more data processing chains of cells is established across the face of the wafer-scale integrated circuit.
A cell may fail its functional testing because of a fabrication fault peculiar to that cell. This kind of fault is well known in integrated circuit fabrication where the result is a rejected chip prior to packaging. In the case of wafer scale integrated circuits the consequences can be more serious.
It is in the nature of wafer scale integrated circuits that certain signals are propagated between cells and certain signals are common to all cells. For example, data signals are generally propagated from one particular cell to another, while the power supply and clock synchronisation signals are generally common to all cells. The common signals are generically known as Global signals and are distributed about the wafer scale circuit on Global lines.
A fault on a Global line can effect more than one cell. For example, a broken or short circuit power supply line can disable not only that cell where the fault physically occurs but also many adjacent cells also dependent upon that particular line for their power supply.
Various schemes have been proposed whereby the effects of Global line faults can be reduced. In particular, power lines can be prevented from disabling more than one cell in the presence of a short circuit by the inclusion therein of fusible isolation links which melt when they carry excess current. Such measures are acceptable in lines carrying sufficient power to melt links and the like, but in the case of other Global signal lines there is not the energy available to achieve such protection.
It is therefore desirable, in order to maximize the number of functionally useful cells on a wafer scale integrated circuit, to maximize the number of low-power Global signal lines thereon.